In figure you can see a simplified diagram of the two integer pipelines contained in a Bulldozer module.
Each of the two cores has a unified instruction scheduler, able to carry out the instructions as soon as the necessary data and execution units are ready. The execution units are 4, two of which are capable of performing address calculation instructions and simple arithmetic logic instructions (Agen), one can perform complex arithmetic instructions, as well as multiplications (Ex MUL) and one can perform complex arithmetic instructions, as well as divisions (Ex-DIV). Each unit is equipped with a 16KB L1 data cache with write-through writing policy and mostly exclusive with respect to the L2 cache, a TLB data cache of 32 pages, fully associative and a load/store unit, completely out of order, capable of performing two 128-bit reads and a 128-bit write per cycle, with a queue of 40 positions for reads and 24 for writes.